Crossing the Threshold

I think today Ray wants us to test the threshold levels produced by the DACs. While I'm waiting for him to get here, I'll keep working on my own TDC code.

After some thought, I think that the pseudo-dual-edge-triggered flip-flops are probably not going to be able to keep up with the (3-inverter) ring oscillators, because of the number of LUTs worth of delay (2 perhaps) in the interface logic (two levels of XOR gates) that turns the two single-edge triggered registers into a dual-edge triggered one. However, I am not 100% sure, especially since the half-adders and the XORs may get compiled together into a single LUT, so I am going to try it anyway. Also, even if we go to a 5-inverter ring oscillator, if we cut that period in half using the PDEDFF, that will be 2.5 inverter delays between active edges, which is still better than 3.

Found RTL_ATTRIBUTES.VHD online, added it to project. I think it is from IEEE Std 1076.6TM-2004, IEEE Standard for VHDL Register-Transfer Level (RTL) Synthesis. However, it doesn't appear that Quartus supports all of these attributes yet.

OK, we verified the ability to set the DAC output levels for the comparator thresholds through the LabView interface. Here is the mapping from LabView VI elements to net names in the PCB schematics/layout and reference designators of the test points:

Designation in vth_test1.vi Header PCB net
--------------------------------- --------- ----------

1. VTH (High) (Low Energy) 2 J37 VTH5
2. VTH (Low) (High Energy) J38 VTH6
3. VTH LOW HS 2 J33 VTH1
4. VTH HIGH HS 2 J34 VTH2
5. VTH 5 J35 VTH3
6. VTH 6 J36 VTH4

Also, we started looking at how to probe the LVDS comparator outputs. Here is an example. We should probably rename the nets in the PCB layout to be more descriptive.

PCB nets Quartus net Pkg. pin Net (PCB) Hdr.
------------- --------------- ----------- ------------ ------

1. PMT_1,VTH1 P1VTH[1] PIN_F17 N9384431 J53
2. ...

Back on the Quartus design now. I have test-compiled the PDE_DFF, PDE_REG, and RING_OSC modules, and am ready to put them into a test circuit in my DE3_GPSAPP project. Oh, first I need to bring in my carry-save counter and integrate it with the PDE_REG. However, I have to go now, so that will have to wait till next week.