Darryl is here, along with the others; getting him set up with accounts.
We tested the parallel cable with the ByteBlaster on Mike's computer (with our programming files from last Tuesday; the 450 MHz counter test); that worked.
Now the guys are installing the ByteBlaster driver on the Acer (Windows 7). Oops, there's a note that says that it doesn't support 64-bit Windows 7, and that's what we have! So now, getting the XP partition up and running again (assuming it's 32-bit Windows) is a bigger priority. Tried booting into Linux, but apparently the bootloader is what is complaining that the files in C:\NST aren't available. We may need to boot off a Linux boot CD. Emailed Juan for assistance. We'll set this aside for now.
After that, I think the first thing they will do today is just add an additional counter probe bit, say bit 32. Meanwhile, I am working on the FIFO_reader module.
Great, bit 32 works - its frequency, according to a scope measurement, is 104.8 mHz, which is 2^32 times slower than 450 MHz.
Top to Bottom: Counter bits 0 (violet), 4 (blue), 8 (yellow), and 32 (green) with horizontal scale set to 40 ns/div (first screenshot) and 2 s/div (second screenshot) respectively.
Now they are working again on the pulse_cap_test module.Spent some time talking with Darryl about the project and going through some of the code.
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