Cleaning House

We were going to have a lunch meeting today, but the place we were planning to meet at was closed.

I'm thinking maybe today I'll build a new project from scratch, as a maximally-clean place for us to work in, so we don't have to deal with all the files and assignment warnings still left over from Sachin's version.  If we need anything from Sachin's design, we can always pull it in.  And, I can make the port names more informative.

Meanwhile, David or Darrell or Tyler (or whoever shows up) can continue to work on the DAC controller.

Once I finish my cleanup, we can reintegrate everything into the new project, and continue working on the C development in there.

Created a new folder C:\SHARED\FEDM_code_v2\q91 to do the cleanup work in.  (Haven't actually shared it yet.)

The device will be Stratix II: EP2S30F484C3.

The design files include (copied from old project's file list):

• [/] COSMICi_top6.bdf
• [/] pulse_gen2.vhd
• [/] hspeed_counter.v
• [/] my_pll.v (plus .inc, .ppf, .qip, _bb.v)
• [/] my_altclkctrl.v (plus .inc, .qip, .v, _bb.v)
• [/] decs_cntr.vhd
• [/] pde_reg2.vhd
• [/] pmt_ic_datapath2.bdf
• [/] pulseform_cap.bdf
• [/] pulse_prep.bdf
• [/] pulse_combine.vhd
• [/] cs_combine.vhd
• [/] pde_dff2.vhd
• [/] pulse_cap.vhd
• [/] pde_dff_en.vhd
• [/] pde_shift_reg.vhd
• [/] pde_dff.vhd
• [/] our_fifo2.bdf
• [/] fifo_writer2.vhd
• [/] pulseform_fifo.vhd (plus .bsf, .qip, _wave0.jpg, _wave1.jpg, _waveforms.html)
• [/] fifo_reader2.vhd
• [/] stream_pulse_data.vhd
• [/] stream_pulse_out_test.vhd
• [/] FEDM_NiosSys.vhd
• [/] cpu_0_test_bench.vhd
• [/] cpu_0_mult_cell.vhd
• [/] cpu_0_oci_test_bench.vhd
• [/] cpu_0_jtag_debug_module_wrapper.vhd
• [/] ... (all cpu_0 files)

Also:

• [/] Symbol (.bsf) files associated with the above design files.
• [/] FEDM_NiosSys.* (all files associated with the SOPC system design)
• [/] jtag_uart_0*.*
• [/] icdp_ctrl.vhd (these 3 are PIOs)
• [/] icdp_data.vhd
• [/] icdp_stat.vhd
• [/] onchip_memory2_0*.*
• [/] uart_0*.*

OK, that's all copied over.  I think that's it, but if I forgot anything I will grab it later.

Now running the New Project Wizard to create the new project.

Working directory:  C:\SHARED\FEDM_code_v2\q91
Project name: COSMICi_FEDM
Top-level entity: COSMICi_FEDM_top6 (renamed COSMICi_top6.bdf to this)
Did "Add All" to add all design files in the folder to the project.
Selected the device.
Finish.

Now, I need to create pin assignments.  Let me refer back to our existing project first.

Currently used pin location assignments are:

• Input clkin_50MHz -> OSC100MHZin -> PIN_AB13 (3.3V LVCMOS) - (Also clock setting)
• Output sys_clk -> TVTH[6] -> PIN_AA17 (3.3V LVTTL)
• Output pd -> FIFO_FULL -> PIN_E12
• Output hd -> P1VTH[6] -> PIN_F14
• Output data[0] -> P2VTH[6] -> PIN_J15 (3.3V LVTTL)
• Output data[1] -> P4VTH[5] -> PIN_G16
• Output data[2] -> P2VTH[3] -> PIN_G15
• Output data[3] -> P1VTH[1] -> PIN_F17
• Output data[4] -> P1VTH[5] -> PIN_F15
• Output data[5] -> P4VTH[6] -> PIN_G14
• Output data[6] -> TEST[6] -> PIN_G13
• Output data[7] -> TEST[7] -> PIN_C12
• Output pf[1] -> PULSE[1] -> PIN_B11
• Output pf[2] -> PULSE[2] -> PIN_C10
• Output pf[3] -> TVTH[5] -> PIN_F9 (3.3V LVTTL)
• Output pf[4] -> TVTH[3] -> PIN_G8
• Output pf[5] -> P1VTH[3] -> PIN_F7
• Output pf[6] -> PULSE[6] -> PIN_H7
• Output tx -> RESET1 -> PIN_AB15 (J49 pin 3)

Let's create new assignments for these, and rename the ports a little more sensibly with reference to the details of the actual board/layout/schematic (in descending order of importance).

• [/] Input clkin_50MHz -> OSC1_p1_50MHz_in -> PIN_AB13 (3.3V LVCMOS)
• [/] Output sys_clk -> J45_p2_GP0 -> PIN_AA17 (3.3V LVTTL)
• [/] Output pd -> J48_p2_GP1 -> PIN_E12 (3.3V LVTTL)
• [/] Output hd -> J55_p2_GP2 -> PIN_F14 (3.3V LVTTL)
• [/] Output data[0] -> J82_p1_GP3 -> PIN_J15 (3.3V LVTTL)
• [/] Output data[1] -> J73_p1_GP4 -> PIN_G16 (3.3V LVTTL)
• [/] Output data[2] -> J74_p1_GP5 -> PIN_G15 (3.3V LVTTL)
• [/] Output data[3] -> J53_p1_GP6 -> PIN_F17 (3.3V LVTTL)
• [/] Output data[4] -> J55_p1_GP7 -> PIN_F15 (3.3V LVTTL)
• [/] Output data[5] -> J72_p1_GP8 -> PIN_G14 (3.3V LVTTL)
• [/] Output data[6] -> J71_p1_GP9 -> PIN_G13 (3.3V LVTTL)
• [/] Output data[7] -> J75_p1_GP10 -> PIN_C12 (3.3V LVTTL)
• [/] Output pf[1] -> J76_p1_GP11 -> PIN_B11 (3.3V LVTTL)
• [/] Output pf[2] -> J77_p1_GP12 -> PIN_C10 (3.3V LVTTL)
• [/] Output pf[3] -> J58_p1_GP13 -> PIN_F9 (3.3V LVTTL)
• [/] Output pf[4] -> J57_p1_GP14 -> PIN_G8 (3.3V LVTTL)
• [/] Output pf[5] -> J54_p1_GP15 -> PIN_F7 (3.3V LVTTL)
• [/] Output pf[6] -> J79_p1_GP16 -> PIN_H7 (3.3V LVTTL)
• [/] Output tx -> J49_p3_UARTTX -> PIN_AB15 (J49 pin 3)

OK, now let's try a compile!  Had a few mistakes, but those were easily fixed.  Timing analysis failed to meet fmax constraints, but the thing works anyway.  The power consumption is up with my current design compared to the students'; perhaps this is just because the Nios system in there, but at some point we need to go through things, like make sure the ADCs and the USB chip are turned off, and that there are no fights on FPGA pins, to minimize board power consumption.

Next, I need to try actually running my C code in the new project (both on startup & under debugger), and redo in it a serial output test like the one I did several weeks ago.

Meanwhile, David is here, and is continuing to write the code for DAC_control.vhd.  He finished the code and we did a test (intending to get 2.5, 2.0, 1.5, 1.0, 0.5, 0.0V) and got ~2.4V on the 1st 3 thresholds, 1.2V on the 4th, and 0 on the last 2.  Then we made a couple of changes (correcting some errors in the timing sequence) and tried again; got (2.4, 2.2, 1.3, 1.2, 0.0, 0.0).  The fact that the maximum value isn't 2.5 isn't surprising, since the board is underpowering the DACs, but the rest of the scale seems a lot more nonlinear than we expected.   But we are getting close.  Next thing to try, tomorrow:  Slow down the timing sequence a little (we are pushing the edge of the spec right now).  Also, examine the control signals on the scope to make sure they appear as intended in the code.

Meanwhile, Darryl arrived and has started working on the DAC CPU interface (under VirtualBox on the center-desk Mac).  He thinks his module is basically finished, but we still need to test it - we'll do that next week.  He can write a simple input driver stub, or we can just try driving it from the C code.

A test driver stub module could do something like this:  Every 50 microseconds, increase one of the DAC levels by 1 (it only takes ~10 microseconds for the programming sequence); then on the scope, that level should rise from 0-2.4V in a sawtooth waveform with a ~200 ms period (to go through all 4,096 levels).