Mon., Feb. 27th

David is here, and I've uploaded my changes from over the weekend to Dropbox (C:\Users\Mike\Documents\My Dropbox\COSMICi_devel\FEDM_design\FEDM_code\q91)

The important files that are new or changed are:

• se_reg_en_56_pip.vhd - Version of this register with pipelined enable signal.
• se_dff_en.vhd - Updated this DFF to use Altera DFFE primitive to try to ensure that enable is really an enable and not a feedback path.
• se_pulse_cap_tsedge_56.vhd - Updated this edge-capture module to use the new register.
• se_pulse_cap_56.vhd - Updated this pulse-capture module to use the new register.
• cscnt_pipeline_register_56.bdf - New 2x56-bit register w/ no reset/enable, to use in pipeline to fan-out 
• tsedge_datapath_v2_56.bdf - Timing edge-capture datapath modified to use new pipeline register at counter input.
• pmt_ic_datapath2_56.bdf - Pulse capture datapath modified to use new pipeline register at counter input.
• pmt_ic_datapath_v3_56.bdf - Pulse capture datapath modified to use new pipeline register at counter input.

Plan for today (for the students):

• Do changes like I did for the high-speed mockup, but in the real design.
• For reference, the high-speed mockup project is at FEDM_code\High_Speed_Mockup.qar on Dropbox.  (Don't expand it within the main folder though.)

I'm checking to see whether using the Altera DFF megafunction registers in the counter pipeline in my working project (Q:\) caused worse performance than in the mockup where I used our own VHDL.  I don't expect it would have made much difference, but you never know.  The technology map for the Altera registers looked kind of strange.

Got 214.96 MHz; same as yesterday.  So it doesn't matter what kind of register we use there.

Some notes on what I put in my LogicLock region yesterday (so I can delete these from my test project):

• *|pulseform_cap_56:*|pulse_prep_56:*|se_pulse_cap_56:*
• This gets all the front-end pulse-capture instances within the 3 main pulseform-capture datapaths.
• hspeed_counter_56:inst22
• This includes both the PLL and the high-speed counter.
• pmt_ic_datapath2_56:inst20|cscnt_pipeline_register_56:inst4
• Pipeline register for counter input in the 1st pulseform-capture datapath.  
• pmt_ic_datapath_v3_56:inst*|cscnt_pipeline_register_56:inst4
• Pipeline register for counter input in the 2nd & 3rd pulseform-capture datapaths.
• tsedge_datapath_v2_56:inst11|cscnt_pipeline_register_56:inst4
• Pipeline register for counter input in the timing-sync edge-capture datapath.
• tsedge_datapath_v2_56:inst11|pulse_prep_tsedge_56:inst2|se_pulse_cap_tsedge_56:inst
• Front-end timing-sync edge-capture module.

Need to tell the students this trick for putting just the desired components into LogicLock, when they're ready for it.

Samad showed me his new design for the power-distribution board - it's much improved, and just about ready to give to Donte for fabrication.

David and Juan cut/stubbed the slow-speed stuff out of one of the pulseform-capture datapaths, and David is going to do the same to the other one (which has two instances).  Aarmondas just got here, & David's going over what we're doing with him, so hopefully Aarmondas can do the same thing with the timing-sync datapath.

Just for a lark, I'm going to try compiling with the high-speed components in a child region of the root region, with Reserved turned on so the low-speed stuff (hopefully) can't interfere with it at all.  I don't think it'll fit, but what the heck, it's an easy enough thing to try.  Huh, it fits!  242.72 MHz.  Better than without it, but still not the best possible.``

What else to work on today?  Finally testing & debugging the new server code to warm-start the GPS?  Sounds good...  Some of the wires on the Wi-Fi board got detached, had to reconnect them...  OK...

Worked through various bugs in the new code (all before the point where we send the warm-start command).  When I stopped, I was just about to implement the as-yet-unimplemented methods wifi.WiFi_Module._uartSrvConnected(), _auxioSrvConnected(), _mainSrvConnected().  (Should be easy; just out of time now.)