Trying to get reoriented...
Darrel & Tyler are here; giving them some tips on the VHDL coding for the output stub module for the pulse form digitizer...
I am currently adding the following PIOs to the Nios SOPC system in my test project in C:\LOCAL\FEDM_gelware\COSMICi-mods\Stratix-TDC-V1:
- icdp_ctrl (Input Capture Datapath Control) - 8 bits, output. For controlling the datapath.
- Bit #0: RUN_PAUSEn - Pause the whole datapath (0), or let it run normally (1).
- Bit #1: PUMP_DATA - Rise = pull next word. Fall = done with word.
- Bits #2-7: Reserved for possible future use.
- icdp_stat (Input Capture Datapath Status) - 8 bits, input, with synchronous rising-edge capture IRQs with single-bit reset for the edge capture register. This will allow the CPU to independently manage interrupts on each of the kinds of events that can occur.
- Bit #0: BUF_FULL - Datapath is stalled b/c FIFO buffer is full (1), or not (0).
- Bit #1: HAVE_DATA - Data is available to be pulled (1), or none is left (0).
- Bits #2-7: Reserved for possible future use.
- icdp_data (Input Capture Datapath Data) -32 bits, input. No interrupts.
The guys got their output module to the point of testing, and identified another 6 output pins to use so that they can display the input pulse alongside the output data.
There is some unexpected high-frequency glitching of the data from the output stub; not yet diagnosed.
There was a misunderstanding about I wanted WRT the output data; that is being fixed.
For me to do tomorrow:
- Import their (the students') input stub (which is working) to my top-level schematic, to feed test inputs into the input capture datapath;
- Start slapping together the C code to drive the PMT input capture datapath, and output diagnostic information to the JTAG stdout, and formatted data to the serial port.
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