Rebecca Black Day

It's a furlough day, and my usual day off this summer, but I was in town anyway to pick up my new (used) car from the transmission shop and run some other errands, so I thought I'd stop by the lab for a bit.

Regarding my old car, I need to call my last note holder before 5 and see if they still have the title, and have them send it to me if so; if not, I need to spend some time digging around in my storage room this weekend, hoping to find it. I will need it in order to sell the car for parts. Looks like I can get at least $389 for it. That'll at least help to cover the cost of the last (fruitless) repair job that was done on it.

Meanwhile, I am almost broke again now, so I need to come up with a way to earn some extra money over the next month or two. Thinking of posting a profile on oDesk.

Later, if I have time to do some work before heading home, here are some things I can work on:

1. Try other waveform generator, for shorter pulse widths.
2. Begin working on hand-optimizing pulse-cap module for increased speed.
3. Finish writing FIFO_READER module.

The 4-ns pulse reads properly as ~1-2 delays of 2.5-ns. Trying now to see if I can get circuit working reliably at 250 MHz (500 Msps). Adding an input buffer to pcaptest to delay the producer handshake for at least 10 ns. This is to make sure the input data bits all have plenty of time to settle down before we latch them. OK, that didn't help.

Now adding a pipeline buffer to the output of the logic that computes when to enable the rise/fall time capture registers. This will effectively increase all time values captured by 1, but will not otherwise affect the results. That fixed the problem! Running reliably at 2 ns now (PLL clock multiplier factor = 5x). Trying 6x = 1.67 ns - that works too. Trying 7x = 1.42 ns - no dice! (No handshake.) Trying (20/3)x = 1.5 ns... (333 MHz, 666 Msps). That gives good values some of the time, but not very reliably.

OK, I have to leave now, but I can check early next week to see if there are any more opportunities to improve performance of pulse_cap module through pipelining. It should be easy - just look for signal paths that pass through more than 1 LUT.