Mon., Dec. 12th

Plan for today: Finish testing the new timing-sync datapath.

Juan says he can come by Friday morning to help with testing.

[.] Ask ECE if they can contribute to the project. --> Emailed Simon; follow up later.

Worked with Darryl and David for a bit to try to diagnose the timing signal problems.  It looks like the received signal is roughly 10x weaker than expected (instead of only the 4x weaker that we would expect from the replicated resistor & capacitor).  We checked some resistor values on the board (50 ohm and 1kohm) to make sure that these were not wrong, and they were correct.  We also checked the voltages on the outside of the GND and +2.5V pullup resistors, and they were correct.  We tried moving the input to PMT1, and there the signal was still about 2x weaker than expected.  We then tried hooking the scope directly to the DE3 output (with 50 ohm cable and 50 ohm input impedance) and this factor of 2x was still there.  For some reason the DE3 board is only outputting a roughly +1.5V amplitude pulse instead of +3.3V as we were expecting.  Perhaps it is expecting a 100 ohm cable?   Anyway, this output is a problem even if we remove the extra resistor/capacitor because our lowest threshold currently is only +1.5V.  However, we could move it a little lower.

Also, there is another problem which we didn't figure out yet, which is that the baseline logic level for the timing signal input seemed to be stuck at +2.5V, even when tied via the 1Kohm pulldown resistor to GND.  I have a theory that maybe there are pullup resistors by default on the 12 FPGA input pins that this node fans out to.  I'm going to try adding the pin assignments for the other pins to make sure this isn't the case.

The pins in question are (from the OrCAD schematic):

• TimingSignal (if it were separate from PMT_3):
         Legacy port      Pin pair             Current input port name
• TDCIN[12]:  K20/K19    --> TDCIN3[0]
• TDCIN[13]:  J21/J20       --> TDCIN3[1]
• TDCIN[14]:  H22/H21     --> TDCIN3[2]
• TDCIN[15]:  H20/H19    --> TDCIN3[3]
• TDCIN[16]:  G22/G21     --> TDCIN3[4]
• TDCIN[17]:  F22/F21      --> TDCIN3[5]  (only one assigned at present)
• PMT_3:
• TDCIN[22]:  W1/W2       --> TDCIN4[0]
• TDCIN[32]:  K1/K2        --> TDCIN4[1]
• TDCIN[33]:  J2/J3           --> TDCIN4[2]
• TDCIN[34]:  H3/H4         --> TDCIN4[3]
• TDCIN[35]:  H1/H2         --> TDCIN4[4]
• TDCIN[36]:  G1/G2         --> TDCIN4[5]

OK, added all those assignments to the New_with_Nios_trim revision of the Q:\COSMICi_FEDM project. Also added the corresponding input ports TDCIN3[5..0] and TDCIN4[5..0] to the top-level schematic COSMICi_FEDM_top13.bdf, although of course the only one of these that is actually used at present is TDCIN3[5] --> pf3[5].  This one tells us when the TimingSignal input crosses the lowest threshold (DAC#6).  TDCIN4[] is just a copy of TDCIN3[], due to the bug in the schematic, and is not useful.

The compile is running now.  It will take a while.  OK, that's finally done.

Burned new design into FEDM's EEPROM.  Hooked up timing sync cable and scope to redo the test of the received timing-sync signal.  However, I just noticed that the SMA connector that I had hand-soldered to the OCXO board came disconnected at some point in the last few minutes of fiddling.  Really, that board needs to be completely redesigned!  So I need to re-solder that connection before I continue.  No time today, so I'll do that tomorrow.