Tue., Dec. 6th

Aarmondas and David finished up the timing sync datapath, we hooked it up to the appropriate input and to stream_pulse_out_test for testing, and are presently recompiling to see if the design still fits.

Meanwhile, I'm recompiling the GPS app from 50 to 25 ns (value of the <traim_alarm> parameter) so I can do another overnight run.  (Last night's run stopped at some point but still got a good 37 MB of data at 50 ns that I can analyze.)  Recompiled Quartus, rebuilt EEPROM programming file (Rev_A.jic), now burning it into EEPROM.

The fitter succeeded.  Some notes:

• Combinational ALUTs:     10,089 / 27,104 (37%)
• Dedicated logic registers:  25,747 / 27,104 (95%)
• M512s:                            188 / 202 (93%)
• M4Ks:                             144 / 144 (100%)
• The new module tsedge_datapath_v1_56 takes:
• Combinational ALUTs:   25
• Dedicated logic regs:       19
• Memory blocks:              none

It looks like the whole thing isn't getting synthesized, perhaps because we are only showing the low 8 bits of each word on output?  Need to look at size again after it is hooked up to new SOPC system.  Anyway, it is looking like it will probably be small.

I could hook it up and do a test, but I really should Dremel down a new SMA connector first so that I don't have to mess with any the existing ones.  Got the connector out, I'll dremel it tomorrow.