Tue., Oct. 25th

David had to study for his exam today.

Darryl is here working on the new architecture diagram for the paper.

Used my solder gun to solder two 20-pin breakaway male pin header strips to the 40-pin header footprint (J2) on one of the currently unused Wi-Fi boards.

Tried the electronics cleaning spray I picked up from Radio Shack to rinse the solder flux & oxidation residue off of the back of the board; then rinsed the area briefly in industrial water and dried with a paper towel.  Leaving it to dry overnight, will test tomorrow.  I went ahead and wired up the connections.  Below are the old (left) vs. new (right) versions of the hand-wired logic-level serial port, for comparison.

Old hand-wired logic-level serial port

New hand-wired logic-level serial port

The color code on the wires in the new version is:

• Black     - Common GND
• Red        - M_TX = 3.3V TxD from Wi-Fi board through wire (to FPGA board)
• Blue       - M_RX = 3.3V RxD into Wi-Fi board from FPGA board
• Orange   - M_RTS = 3.3V RTS (req. to send) HW handshaking (flow control) from Wi-Fi thru wire to FPGA
• Green     - M_CTS = 3.3V CTS (clr. to send) HW handshaking (flow control) into Wi-Fi board from FPGA
• Yellow   - M_DSR = 3.3V DSR (data set ready) status input into Wi-Fi board from FPGA - Used to enable autorun (when high).

The old version had all 9 pins of the extra DE9 socket wired up (not just 6), but the others were basically unused.  Also, the old color code was not as informative, because the wire-wrap wire I used in the original hookup had only 3 colors (red=output, blue=input, white=ground) plus one extra orange wire for a +5V power input on the RI line (which was anyway unused).

The new version has no DE9 socket on it, but what I'm thinking is to just do away with the serial cable and connect the other end of the F-F jumper wires directly to the pins in the GPIO1 header or the DE9 connector on the other end (on the FPGA board).

Looking at the photo of the new connector from home just now, I think that pins 10 & 11 might be swapped with each other.  Need to double-check against the Wi-Fi board schematic when I get to work. Actually, looking at the module datasheet, it looks like it is the old version of the connection that is wrong, connecting DSR to a GND pin!  Ah, but DSR was disconnected at the other end, I think (I hope!).  So how did the Wi-Fi board do autorun?  Maybe the M_DSR input has a pullup resistor.  Anyway, we should hook this up properly!  It would be a good idea to run an experiment to make sure that whether the FPGA does autorun really depends on whether DSR is asserted on the FPGA side.