Capture of the Inputs

This week my goal is finish implementing and testing the input-capture datapaths for the PMT inputs as well as the APD input. Below is the (greatly simplified) datapath for the APD input which provides the 409.6-us-period timing sync pulse. The pulse input capture module here can be the same as the one for the PMT input capture datapaths. But, because there is a guaranteed delay between subsequent pulses, we can do away with the FIFO, and rely on the CPU responding to the PIO edge-capture interrupt immediately after each pulse arrives, before the next one arrives.
First today, I got the pulse_cap.vhd module to the point of compiling, at least up to block symbol generation.

Next, Tyler and David were here, and they worked on getting the PLL+DECS counter ready to test on the FEDM board. We verified that bit 4 and bit 8 worked at up to 450 MHz PLL frequency (900 MHz count rate). This gets us very close to the desired 1 ns resolution (actually it is 1.11 ns), but it can perhaps be further optimized.

Later on, we should test additional counter bits, up to at least, say, bit 32. (At 900 MHz count rate, bit 32 should have a period of 9.54 seconds.)

Mike is ordering the SMA connectors which we will need for board testing.