Serial Savior

Adding the Sparkfun level shifter (powered by the +3.3VDOWN net, for LVTTL compatibility) to the FEDM serial port fixed the serial communication problem I was having yesterday. Did a successful output test at 9,600 baud. Recompiling gelware now for 57,600 baud. Not going to bother trying 115,200 baud, since I experienced intermittent problems with that speed previously (in the GPS-->DE3 link). Yes, 57600 works as well. Cleaned up the types/names of the serial port bits in the top-level gelware schematic.

David is here and working towards testing the PLL fast clock and DECS (dual-edged carry-save) counter on the FEDM. Tyler has a family emergency & will be here next week. I haven't heard from Darryl lately-if we don't hear from him soon, we may have to proceed to the next student on our list.

David and I are working to identify pins for viewing the high-speed clock output. Mike referred back to the fabrication drawing for instructions about how to identify controlled-impedance traces. We found a 6.5 mil controlled-impedance (50 ohm) trace going to 2-SIP header J79 pin 1 (FPGA pad H7), and a 5-mil controlled-impedance (100 ohm differential impedance) dual trace pair going to 2-SIP J77 (pin 1+2; FPGA pads C10 & D10). Using ball H7 we were able to confirm a 250 MHz output frequency from a 5x PLL on the scope (although the signal was highly distorted and not full-swing; probably in part because we didn't have a proper 50 ohm probe on it). However, when we tried looking at the same signal as an LVDS output on C10/D10, it was too noisy to even measure its frequency with any confidence. Perhaps shielding would have helped. Basically I think the problem is, we don't have probes capable of measuring LVDS signals. We should probably give up on directly measuring really high-speed signals from this board (anything over a couple of hundred MHz).

We did these tests from Mike's Dell Precision, since the ByteBlaster cable plugs into a parallel port, and the Acer doesn't have a parallel port. Mike ordered a USB-to-parallel cable from Buy.com (under $10) and this will enable David (and/or the other students) to run tests directly from his computer in the future.

Anyway, David's first job for next Monday is to look at the slower counter bits (bit 4 and bit 8) on the scope using some of the available pins that we identified today. Those should enable us to verify both the PLL output frequency and whether the counter is working. He can run the experiment to find the maximum speed at which the counter still works. Then, he can also work on porting the input capture circuit over as well. I explained to him about metastability and the likely need for synchronizer stages in a circuit like this that samples an asynchronous input.

After David left, I spent some time thinking about the design for the input capture circuit. It needs to use the PDE flip-flops. It should probably include a simple state machine which waits for and captures both the leading and trailing edge of the pulse, in case they occur in quick succession. Then it can signal to a consumer that the data (four 64-bit words, sum and carry bits for each of two 64-bit leading and trailing edge times, in units of the doubled fast clock) is ready, and when the consumer signals that the data has been consumed, the IC circuit can resume looking for the next pulse.

The consumer of the data can be another state machine with ordinary (single-edge-triggered) flip-flops with (say) a 50 MHz (20 ns) clock, which takes the data from the IC circuit and stuffs it into a FIFO. At the other end of the FIFO can be yet another circuit which passes the data to a set of eight 32-bit PIOs for the CPU to consume. Another PIO could signal back to this machine when the CPU is ready to consume another pulse. Alternatively, I could check whether there is a FIFO device that already can talk directly to the Avalon bus fabric.

Also, the sum and carry bits could be added together inside one of the 50 MHz state machines (the one at the tail end of the queue, say), thereby cutting the number of PIOs needed down to four, and cutting the memory requirements of the FIFO in half.