Today, we successfully got our test bench working for the pulse waveform input capture circuit, at a PLL clock speed of 250 MHz (which gives us a sampling rate of 500 Msps with the dual-edge triggered front-end modules). This achieves a time resolution of 2 ns, which meets our goal of a time uncertainty (imprecision) of within +/- 1 ns (just barely!).
The logic was actually already correct at the end of the day yesterday. Today, we just honed in empirically on the maximum PLL frequency still producing reliable results (with no glitches cased by register setup time requirements not being met). Also, Mike rewrote David's input stub to make it easier to modify the delay between pulses.
Here is a video showing correct results for "fake" comparator outputs modeling sawtooth-shaped input pulses crossing anywhere from 1 to 6 threshold levels.
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