It is Saturday, but today at home I wrote the code for the new single (rising) edge-triggered version of the front-end modules of the input capture datapath, and uploaded them to the "FEDM_code backup" folder on Dropbox. They have not yet been tested or even fully compiled yet, but they pass symbol generation (superficial syntax checking). The changes were very simple (although many files were affected by them), so I'm expecting that the new version may very well work just fine, hopefully without any debugging needed. I set the PLL output frequency to 500 MHz, which is our goal. We'll see if it's achievable (probably not). Hopefully we can at least push somewhat above 300 MHz, thereby improving on the performance of our present 150 MHz dual-edge-triggered front-end.
One advantage of this set of changes is that the synthesized circuits should now be easier to read... Which will make it easier for us to go through them looking for opportunities to further optimize their performance.
Came into the lab (somebody let me in) to try it out. It works, at 500 MHz! Sweet!
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