Thursday, January 26, 2012

Thu., Jan. 26th

Ray asked me to focus on installing PADS on Friday.  Meanwhile, hopefully Darryl can help continue debugging the timing-sync edge-capture datapath, and Juan can finish up the new firmware code needed to support it.  Hopefully we will be ready to test everything either late Friday or Monday.

George will also come by Friday and show me his copper heat pipe.

On or before next Tue., Jan. 31st, we are supposed to attain a major milestone, which is to demonstrate transmission of absolute time-referenced shower data (for coincidences involving all 3 paddles) to the server, using the present (200 MHz) version of the datapath.

After this, the next milestone deadline for the ECE students is Wed., Feb. 29th, by which we want to demonstrate the above again, but this time using the optimized (500 MHz) version of the datapath (accomplished with help from LogicLock and possibly other hand-optimization).

To help in the planning for this activity, here are some suggested intermediate milestones, and deadlines for them.  (If we do not meet these intermediate deadlines I think we would be hard pressed to achieve the overall milestone by its due date.)

  • On or before Wed., Feb. 8th:  Demonstrate the 56-bit high-speed counter running at 500 MHz, and with all its components logic-locked into placement locations.  Optional: By then, demonstrate 600 MHz speed or higher, possibly using pseudo-dual-edge-triggered registers.
  • On or before Wed., Feb. 15th:  Demonstrate the 56-bit high-speed counter together with the front-end module of the timing-sync edge-capture datapath, both running correctly at 500 MHz with all components logic-locked into placement locations.  Optional:  Demonstrate even higher speed, maybe by using PDE registers.
  • On or before Wed., Feb. 22nd:  Demonstrate the 56-bit high-speed counter together with the front-end modules of all four datapaths (1 timing-sync edge-capture + 3 pulseform-capture channels), all running correctly at >=500 MHz with all components logic-locked into placement locations.
  • On or before Wed., Feb. 29th:  Add all the slower-speed components back in, show everything still fits, demonstrate full system operation at the new higher speed.  (Cooling solution may be necessary by this point.)
Considering power supply issue.  We might be able to use our existing supply if we utilize more of the pins on it.  Did a little research on this, then emailed the following results to Samad:

Samad, here's a webpage explaining power supply connectors:


The big connector upstream of the one we've been using is the ATX 20+4 pin connector.  I compared wire colors and this is correct.  If you look at the table of pinouts above, you will see there are several additional +5V outputs besides the one we are currently using (pin 22).  So, it looks like if you build a power supply board that interfaced to this connector, you would have enough current capacity to power everything (although you should compare the power specs on this webpage against our needs to make sure).  If I were you, I would shop on Digi-Key for the appropriate header to mate with this connector and mount on a printed circuit board.  Then we can design a new power distribution board in PADS and solve our power problems.

Tested timing sync datapath with last night's mods to Darryl's output stub.  Still screwy.  I sure don't see anything that could be wrong in the earlier modules.  Playing around with Darryl's code some more.

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