Tue., Jan. 10th

To do today: Modify firmware to set the last DAC level to +300 mV for detecting the timing-sync edge crossing.

David is out sick, but Darryl is here.  He is looking at some Altera online courses.

Have to leave a little early this evening to go to the entrepreneur workshop.  I guess.  (Not very excited about going.)

License server is not running, or not serving our floating licenses.  Starting LMTOOLS and re-reading license file.  Now the license server is up.

Examined the layout and the board carefully looking for things that might account for DAC #2 failing as well as the 10 ohm short between +2.5VCC and PMT_3.  I noticed on the layout that PMT_3 passes underneath the chip for DAC #2.  Also, it crosses right underneath a pad of C139 which is part of the +2.5VCC node.  A hole between layers in either location might account for the 10 ohm short (since DAC #2 is powered by the +2.5VCC supply).  However, peering closely at both parts thru multiple magnifying lenses, I didn't see anything that was clearly suspicious. You can't really see underneath the parts, anyway.  However, just in case, I blew on both parts with the dust remover spray (1,1-difluouroethane, from Radio Shack) - who knows, this might get rid of a bit of grit wedged underneath the chip.  Obviously this is just a desperation maneuver, and I don't expect it will necessarily help.

Tidied up a couple of slides for the workshop, which is tomorrow at 2.  Earlier today I emailed Aarmondas asking him to reserve a room.

I'm now modifying the init_dacs() function in dac_driver.c, to set the last threshold to +300 mV.  The others are still arranged in a logarithmic ramp from -200 mV to -1V, although now with one fewer step.

Compiled new code in Eclipse.  Compiling it into Quartus design.

CTU is connecting/running fine today, aside from no satellites acquired (unsurprising since GPS is cold-booting).  We probably really need to get a new GPS module that can connect more quickly.

Ah, I just remembered, due to the 10 ohm short between PMT_3 and +2.5VCC, when the power is on, that node floats at +2.5V instead of at GND.  Therefore, the timing sync pulse has to be a negative pulse.  That is accomplished easily enough by a NOT on CLK_OUT in the Quartus design for the CTU.

This means (on the good side) that we can go back to the 5 thresholds we had previously, and just re-use the first (-200 mV) threshold for the timing sync input.

Made those changes, now doing the Quartus recompile.  Have to leave now though.