I brought into the lab the parts I picked up at Staples and Radio Shack last night - a replacement cartridge for the Brother P-touch labelmaker, some premium (high-strength) electrical tape, some speaker wire (for powering the detectors), intercom wire (a possible alternative to jumper wires for interconnections on the main board), and some "telephone spade lugs" for an improved connection to the screw terminals on the FEDM board.
I checked the result of the compile that Mike Dean started yesterday (high-speed entity only), and it was too low - under 250 MHz. Something must be wrong in the design or the compiler settings, because we know we can get over 300 MHz (we are doing so now, in my current version of project w/o the refactoring). I checked the compiler settings and adjusted the placement/routing effort to the values that have been working best for me (4.0 and 1.0 respectively). I also noticed a bunch of extra components were in the LogicLock region, so I deleted all the LogicLock settings and am compiling just the high-speed entity now without LogicLock to make sure that something about LogicLock isn't interfering with getting an optimal compile. If this still doesn't get us at least back up to the neighborhood of the ~350 MHz speeds we were getting before the refactoring, I will have to delve into the design to see if there are any mistakes (i.e., differences in logic (as opposed to organization) from the original design).
One thing I also want to do today is continue straightening up the cabling on the main board - fastening cables down, etc., labeling components, and testing power via Samad's board.
I also need to take a look at the GPS datasheet and see if there is any information there that might help me figure out how much attenuation of the satellite signal the module can tolerate; this is needed to determine how many repeaters we might need (depending on the length of the path at CLC and the gain of the receiving antenna).
By the end of the day, I got Samad's board successfully powering the whole system. Here are a couple of photos:
Regarding the Quartus design: The compile I started earlier in the afternoon still ended up only at under 250 MHz. We know this can't be right (if the design is correct) because the present design is running at 300 MHz (with an Fmax of about 350 MHz). So we are going to have to go through the design looking for mistakes.
I also need to take a look at the GPS datasheet and see if there is any information there that might help me figure out how much attenuation of the satellite signal the module can tolerate; this is needed to determine how many repeaters we might need (depending on the length of the path at CLC and the gain of the receiving antenna).
By the end of the day, I got Samad's board successfully powering the whole system. Here are a couple of photos:
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| Main electronics platform; all components powered through custom power distribution board. I have labeled all the major components and started binding up wires with cable ties and fastening down wire bundles with electrical tape. |
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| Custom power distribution board, designed by student Samad Nurideen. Fabricated at the ECE Department PCB shop by Mr. Donte Ford. Assembled by Samad Nurideen. |
Regarding the Quartus design: The compile I started earlier in the afternoon still ended up only at under 250 MHz. We know this can't be right (if the design is correct) because the present design is running at 300 MHz (with an Fmax of about 350 MHz). So we are going to have to go through the design looking for mistakes.
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