Testing the new RO

Ray wanted to test the comparators today, but we decided that since we expect them to work anyway, we might as well hold off on that until needed to help diagnose any problems we might run into with the actual TDC readout. But figuring out the TDC output will take a more focused effort by Mike over several weeks. Mike will start on that after the end of the semester (i.e., after this week, since it is still finals week).

In the meantime, I am continuing to work on testing our own ring oscillators on the DE3 board. To count (half-) cycles, I wrote a 64-bit dual-edge-triggered carry-save counter in structural VHDL, using the recursive dual-edge triggered register I wrote earlier. I'm not sure if the counter will be able to keep up with the ring oscillator (quite possibly not), but if not, I can back off to a larger size of ring oscillator (e.g., 5 stages instead of 3), and still do a little better (in terms of time resolution) than I could with a single-edge-triggered counter. Anyway, we will see.

Created a simple schematic module test_ro.bdf that just uses the ring oscillator to drive the clock of the 64-bit counter. Having some problem now compiling my recursively generated register (pde_reg.vhd)... Aha, it was just some confusion between parent/child signal names in the recursive port map. Fixed it by passing the I/O through internal signals with different names.

I'm looking at bit 30 of the counter on the scope; this should have a period that is 2^30 (about a billion) times longer than the ring oscillator period. (Because I am using the dual-edge triggered flip-flops, bit 0 of the counter should have the same period as the ring oscillator, and bit N has 2^N times longer period.) Unfortunately, I am seeing nothing on this signal (no change; constant 0). Trying ring oscillator length 5 stages: Still no dice. Now trying 7 stages: That works. Hm, I think this means I have to revert back to single-edge-triggered flip-flops - the dual-edge triggered ones aren't buying us anything.

OK, with the single-edge-triggered flip-flop, and a 3-stage ring oscillator, bit 20's period is 3.75 ms. Thus, bit 0's period is 3.58 ns. Thus, the actual clock period is 1/2 this, or 1.79 ns. Thus, the ring oscillator frequency is 559 MHz. No better than I saw on the DE2! Maybe I should try imposing some time constraints, or something... Anyway, do that tomorrow...