Weekend Thoughts

I started thinking about the project today, and had an idea.

Presently one of the major sources of error we are dealing with in our time measurements is the quantization error due to the fact that we are only sampling the PPS signal from the GPS at 100ns intervals. The standard deviation of the resulting phase error is 100/sqrt(12) = 28.9 ns.

Meanwhile, the GPS module itself uses a 16.368 MHz clock, which means the phase noise due to the quantization error in that clock is less, probably 61.1/sqrt(12) = 17.6 ns.

We could reduce our contribution to the phase error in half if we use dual-edge flip-flops to sample the signal every 50 ns; then the RMS phase error will only be 50/sqrt(12) = 14.4 ns.

However, we could do better yet if we implement our own TDC directly on our FPGA board. Spent some time today trying to do this with the DE2 board I have at home...