One Ring to Rule Them All

Much of this week was shot due to needed car repairs. My timesheet got turned in late, so, no $ next payday... :(

I have to leave early today to pick up Colin, so I'm not sure I have time to accomplish much...

I was planning to look at how/whether I can set delay constraints in Quartus, to see if I can get my ring oscillators to run any faster...

It looks like you have to do it in a Tcl script. There is a command "set_net_delay" which allows you to set a minimum and maximum delay between two nets. I might also be able to use the TimeQuest Timing Analyzer GUI - checking that out now.

Generated a "Net Timing" report for the ring oscillator. The report gives an average Node 1->2 delay of 0.127 ns. Node 2->3 is 0.128 ns. And node 3->1 is 0.117 ns. All together, the total half-cycle period for a ring oscillator transition should be 0.372. So, a full cycle should be 0.744 ns, implying the ring oscillator frequency should be 1.34 GHz! This is more than twice the frequency (~550 MHz) that I actually observed, so something is fishy.

OK, I'm looking now at the ring oscillator layout in Chip Planner, and it appears that all 3 of the inverters have been synthesized in a couple of cells that are located right next to each other. So, Quartus is already doing as best it can to minimize the ring oscillator delay. The only question is, why does the actual ring oscillator frequency turn out to be only about half as large as expected? Perhaps I need to double-check my measurement setup with the carry-save counter, or try to figure out if I can do a more direct measurement of the ring oscillator output, perhaps through the CLK_OUT coax connector. Let's try that early next week.