De bug! De bug!

Temporary jury-rigged cooling setup for our FPGA board.

Today I need to debug the problems with my new project.  We have two major issues at the moment:  (1) Test bench for the IC datapath no longer working reliably after a little while; (2) DAC outputs not right.  The verification problem in Nios IDE went away by itself (this time at least). 

• Theory: (1) could be a timing problem that manifests at higher temperatures, due to overheating at higher power level caused by the Nios core.  Try cooling, slowing down system clock.

I tried slowing down the clock by 2x.  This fixed the problem with the test rig for the input-capture datapath (but not the DAC problem).  Then I placed a couple of metal blocks on the board (on the FPGA and the main voltage regulator) with a thermoelectric cooler on the FPGA block.  I will see if this allows me to turn the clock speed back up.  It seems to help, but the DAC controller is still having the same problem.  What is weird is it gets the right value while programming the next design into the FPGA (as soon as the .sof file starts downloading)!

I brought in a nail file today, and filed down one of the SMA connectors to where it fits OK in its thru-holes.

Successful test of the CPU interface to the DAC controller.
The input stub generates a voltage ramp from 0 to +2.4V.

Back to the old project.  Darryl arrived and coded up a new input stub "dac_CPU_test.vhd" and wired it up.  We found a few bugs in it and fixed them.  After that, his dac_cpu_if.vhd module worked perfectly, generating the desired voltage ramp!  Congrats to Darryl on writing a module that worked perfectly on 1st test!  That is a real milestone for any programmer.

David and I looked back at the DAC_control module again to see if we could figure out what might be causing it not to work properly in the new project.  We didn't see anything obvious.  But, next we'll try initializing the output signals on first load to see if that helps.

Now that we know they work, I should also try importing the CPU interface and input stub into my new project...  Maybe for some reason, they will succeed where programming the default levels failed...