Fri., Mar. 9th

To do today:  Debug new rising-edge time-capture datapath in CTU.  Yesterday it was not triggering interrupts.  The datapath could be stalling.  The raw counter bits appear to be working (3 of them, bits 24-26, are sampled on blue LEDs).

Added current-state bits of the rise-cap module as an extra debug output from the high-speed logic module.  Still need to wire them to an output port...  Also wiring up the handshake signals from pulse-capture to cs-combine.

Weird; no state change, no handshake.  Added taps for reset and enable signals.  Enable never goes high!  But why?  Tapping out 5 bits of the rise_sum register (bits 27-31), these bits should change every second.

After adding all these diagnostics my Fmax crept back below 350 MHz at some point.  Changing PLL speed temporarily to 300 for debugging.

OK, now it's working (although still not very reliably, and I still don't see anything on the scope) - seems like I have to try a more or less random sequence of STOP/GO/START/RESET/RESTART commands to get it to actually capture & count PPS pulses.  And even then, the datapath still seems to get hosed after a while to where it no longer responds.

Took the reset/enable out of the synchronizer chain for the PPS input; it's possible that was causing some problems due to the possibility of coming out of reset in the middle of a (half-second-long) PPS high period and perceiving that as a rising edge.

I think it might be fixed now; not sure though; needs more testing.

Now trying to get Fmax back above 350 MHz, with the PLL compiled at 350.  Did the thing of declaring other modules empty temporarily, then adding them back in.  Cool; now it's saying 376-408 MHz.  (Weird that it's faster.)  Wonder if it's worth trying 375 MHz as the PLL speed?  That would correspond to 750 Msps or a 1.33 ns resolution.  Perhaps we shouldn't get greedy, though.  Make sure this works first.

Duh, figured out why the scope wasn't reading anything - the digital read-in cable just wasn't plugged in all the way.

The thing seems to be working fine at 350 MHz.  This would be a good time to backup the project.  OK, it's copied to local file C:\LOCAL\Quartus_projects\q9v1sp2\GPS_FPGA_app.

With PLL @ 375 MHz we're now getting Fmax = 371-400 MHz.  We didn't quite make it at the hot corner, but I'll try it - it may work anyway since the junctions are unlikely to be as hot as 85 C.

Tested & works @ 375 MHz!  So we are now at 750 Msps sampling rate (or counts per second), a.k.a. 1.333 ns time resolution (a.k.a. +/- 0.67 ns maximum time measurement error).