Also doing top-level wiring of Nios core. I had to modify the PIOs a bit, because I am now using a separate producer-consumer handshaking signal pair to communicate with cs_combine_56_re and the CPU. (Previously the CPU got interrupted whenever the low word of the PPS rise-time register changed.) Also, the data width is now 56 bits instead of 48. Making corresponding firmware changes as well. The new time-capture performance should be 700 Mcps (million counts per second) as opposed to the 10 Mcps we were getting previously, for a 70x improvement.
Oops, the speed of my logic-locked components wasn't preserved! Perhaps because I forgot to turn on "Compilation Process Settings --> Incremental Compilation --> Compatible Placement and Routing". Blah.
OK, let's try it again. Remove the high-speed thingy from Logic Lock, delete all the low speed stuff, recompile, put it back in logic-lock, recompile, turn on compatible placement/routine, add high-speed stuff back in, recompile, done (hopefully). If that doesn't work, then we might have to look into creating design partitions.
Maybe I'll go ahead and try the partitions thing. You just do Alt-D to bring up the Design Partitions window. Then you drag the module into <<new>> and it creates a new partition for it under the top partition. Under "Compilation," we set Netlist type to Post-Fit and set the Fitter preservation level to "Placement, routing, and high-speed tiles" for maximum preservation.
I'm not yet sure whether it's also necessary to move all the other components into a different partition. Let me do that anyway, just in case.
Aha, I think I found a key. Set the other partitions' Netlist type to "Empty", which puts placeholders in place of them. This beats the hell out of all the manual crap we were doing before.
Getting closer! 338-367 MHz. Let's see if we can get the slow corner up. Put the IOV module into its own empty partition, and try 4.0 placement effort multiplier.
YES!!! 362.58 MHz (hot) to 393.39 MHz (cold).
Next, we'll put the high-speed module into the root Logic Lock region (is this even necessary?), and recompile with just that change - based on past experience, this should give the same result. It did.
Then, we'll tell the Partitions thingy to please preserve the post-fitting netlist with all placement and routes for the high-speed module and change the other modules to non-empty.
Success! Fmax was exactly preserved after adding all the other components back in. The timing analyzer is complaining in red that setup time constraints are violated for signal paths crossing between timing domains, but that's not a "real" error, since this is accounted for in the design. There's probably a way to tell it to ignore those paths, but no biggie.
Next up, I guess, is testing. I doubt everything will work perfectly (I made a lot of changes with no testing yet), but I suppose it's worth a quick try.
Ah, the counter LEDs flash after "HOST START," but there is some bug with the way I am fiddling with control bits. I think I've fixed that now. Let's try the new firmware within the IDE.
There's still a problem somewhere - I suspect with the interrupt setup. Lights flash and main loop responds, but no PPSCNTR messages after the initial one.
Hm, checked over the interrupt-related code and it all looks good. So maybe the problem's not there after all. Too bad.
Oh well, there might be a bug somewhere in one of my new gelware modules. We'll do some lower-level debugging another day.
I'm not yet sure whether it's also necessary to move all the other components into a different partition. Let me do that anyway, just in case.
Aha, I think I found a key. Set the other partitions' Netlist type to "Empty", which puts placeholders in place of them. This beats the hell out of all the manual crap we were doing before.
Getting closer! 338-367 MHz. Let's see if we can get the slow corner up. Put the IOV module into its own empty partition, and try 4.0 placement effort multiplier.
YES!!! 362.58 MHz (hot) to 393.39 MHz (cold).
Next, we'll put the high-speed module into the root Logic Lock region (is this even necessary?), and recompile with just that change - based on past experience, this should give the same result. It did.
Then, we'll tell the Partitions thingy to please preserve the post-fitting netlist with all placement and routes for the high-speed module and change the other modules to non-empty.
Success! Fmax was exactly preserved after adding all the other components back in. The timing analyzer is complaining in red that setup time constraints are violated for signal paths crossing between timing domains, but that's not a "real" error, since this is accounted for in the design. There's probably a way to tell it to ignore those paths, but no biggie.
Next up, I guess, is testing. I doubt everything will work perfectly (I made a lot of changes with no testing yet), but I suppose it's worth a quick try.
Ah, the counter LEDs flash after "HOST START," but there is some bug with the way I am fiddling with control bits. I think I've fixed that now. Let's try the new firmware within the IDE.
There's still a problem somewhere - I suspect with the interrupt setup. Lights flash and main loop responds, but no PPSCNTR messages after the initial one.
Hm, checked over the interrupt-related code and it all looks good. So maybe the problem's not there after all. Too bad.
Oh well, there might be a bug somewhere in one of my new gelware modules. We'll do some lower-level debugging another day.
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