- [ ] Do a test run with new FW burned into FEDM. - Last night's Quartus compile stalled. Finished it up. Burned it onto board. Got a high rate of garbage output - looks like PLL was set at 500 MHz. Turned it down to 250 MHz (slightly above hot-corner speed of ~249 MHz) to see if that works; recompiling now. Quartus keeps crashing! I think my incremental compilation settings are confusing it. More below.
- [/] Ray should drop by after his class to sign timesheets. Get it signed & turned in to Sonja. - We signed 'em and David ran 'em over.
- [/] Reserve rental car for SEALER trip. - Done (Avis), printed confirmation. Hope they don't need a credit card - maybe I should call them later. OK, the terms on the reservation say they do take debit cards at this location. Printed out terms to bring with me in case there's any question.
- [/] Installing Quartus on laptop. - Got full 91 base; adding SP2 now.
* Juan/Aarmondas's "high speed" partitions had some extra stuff in them. Mike Dean is fixing that. He also stubbed out the 6th pulse_prep in each pulseform-capture datapath to make more space & is putting the pipeline registers back in.
* I discovered that you can merge partitions.
* Seems to be necessary to use LogicLock also (not just partitions) to preserve performance - I tried using partitions without LogicLock, and Fmax slowed down when I added the less performance-critical logic back in.
* I tried dragging the merged partition into the LogicLock region, but it seemed to only add one instance. I went through and added all the high-speed instances to the LogicLock region using wildcards. Hope I did it right.
* After adding the slow-speed logic in Top to the merged partition, Fmax slowed down again to 300-something. Guess I could go ahead and burn this version since I'm only asking for a PLL speed of 250 at the moment.
* Quartus has been acting really odd today. It keeps hanging at specific places. Maybe I need to reboot.
* Rebooted desktop; also copied Q:\ contents to laptop (under my desktop in q91sp2\FEDM\). Amazingly, Quartus seems to run significantly faster on my new laptop than it does on my desktop! Maybe it's the combination of the i3 processor and the SSD.
* Michael Dean left Quartus compiling under VirtualBox - this is a test of the logic-locked high-speed logic, in a post-fit (strict) partition preserving placement & routing, with the slower-speed stuff added back in around it. Unfortunately, the Fmax at the hot corner only came out to 311.92 MHz. So, something is still not right. Did we forget to include one of the modules clocked by the PLL clock in the stuff that is included in the partitions & the LogicLock? It looks to me like he got everything, although someone else should probably double-check.
One thing though: The pulse_cap modules for the 6th threshold could be removed from the partitions and the LogicLock, since we are not using them anyway. This might help - since it reduces the number of instances of that module from 18 to 15, and makes the fitting easier. (Those modules aren't getting automatically eliminated, since they are locked in.) I actually did this in the copy I'm working with on my laptop -- we'll see how that compile comes out. - That one yielded 324.04 MHz; a little faster but not much, and still far from our 500 MHz target. We'll have to play with it more another day.
Another thing to try: Turn the fitter placement effort from the default 1.0 up to 4.0. This helped (and seemed to be necessary) in my DE3 GPS app. It's worth trying in the FEDM code as well. Of course, this will make the fitter run even slower than it does now, but hey... You gotta do what you gotta do.
Currently, placement and routing effort are set at 2.0. I found in the other project that it actually did worse at 2.0 than it did at 1.0; but then it got better again at 4.0. The same might be true here.
* Quartus has been acting really odd today. It keeps hanging at specific places. Maybe I need to reboot.
* Rebooted desktop; also copied Q:\ contents to laptop (under my desktop in q91sp2\FEDM\). Amazingly, Quartus seems to run significantly faster on my new laptop than it does on my desktop! Maybe it's the combination of the i3 processor and the SSD.
* Michael Dean left Quartus compiling under VirtualBox - this is a test of the logic-locked high-speed logic, in a post-fit (strict) partition preserving placement & routing, with the slower-speed stuff added back in around it. Unfortunately, the Fmax at the hot corner only came out to 311.92 MHz. So, something is still not right. Did we forget to include one of the modules clocked by the PLL clock in the stuff that is included in the partitions & the LogicLock? It looks to me like he got everything, although someone else should probably double-check.
One thing though: The pulse_cap modules for the 6th threshold could be removed from the partitions and the LogicLock, since we are not using them anyway. This might help - since it reduces the number of instances of that module from 18 to 15, and makes the fitting easier. (Those modules aren't getting automatically eliminated, since they are locked in.) I actually did this in the copy I'm working with on my laptop -- we'll see how that compile comes out. - That one yielded 324.04 MHz; a little faster but not much, and still far from our 500 MHz target. We'll have to play with it more another day.
Another thing to try: Turn the fitter placement effort from the default 1.0 up to 4.0. This helped (and seemed to be necessary) in my DE3 GPS app. It's worth trying in the FEDM code as well. Of course, this will make the fitter run even slower than it does now, but hey... You gotta do what you gotta do.
Currently, placement and routing effort are set at 2.0. I found in the other project that it actually did worse at 2.0 than it did at 1.0; but then it got better again at 4.0. The same might be true here.
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