Was in lab from about 3:30 - 4:30. Darryl & David were there. David is downloading Quartus to his Windows XP installation under Parallels on his Mac laptop - the first version he tried didn't work, so he is trying another one. Meanwhile Darryl is experimenting with LogicLock on his laptop. He says that the timing analyzer gets an fmax of 611 MHz for the high-speed counter by itself, which is in line with the experiments we did last year (we had successfully run the counter by itself at 600 MHz). It might also be worth trying the dual-edge triggered one again. Alternatively, we could effectively double the frequency to 1.2 GHz by just using the clock signal itself as the low bit of the counter (but in order for that bit to actually be measurable, we'd have to have a double-edge-triggered version of the pulse-capture circuit that runs at that speed).
I added Darryl & David to the group on Blackboard to help them coordinate with the Senior Design students using the group email, group blog, etc. I also wrote a message to Aarmondas asking him to please coordinate a schedule for the ECE students Juan & Michael Dean to be in the lab working with Darryl & David on the Logic Lock stuff.
Some things for me to do on Monday:
[ ] Try installing the Service Packs (SP1 & SP2) for 9.1 to facilitate letting us all use the shared network drive Q:\ (\\COSMICi\shared\FEDM_code\q91). The downloads should have got finished before I left Wednesdeay.
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