Monday, February 20, 2012

Mon., Feb. 20th

Over the weekend, I rescheduled the weekly advising meetings with the Senior Design students to Thursday @ 9:30 am (from same time Tuesday) to help Juan avoid a time conflict with his RA job.

David got email assistance from Altera for his issues installing Quartus under Parallels on his Mac laptop; he is downloading the correct version now, and he says he will be here starting at 2:00 pm.  Hopefully, some of the Senior Design students will also be here so that he can help them work on the LogicLock task.  Juan is here now.  He is currently planning to work 12:00 - 4:00 pm Mondays and Wednesdays and to work in the science library if the lab is not open when he gets here.  We noticed that the "COSMICi Calendar" was not visible to him for some reason.  I explicitly gave each of the project members access to this calendar, and emailed instructions for accessing it to the group.  David has now added his hours there as well.  Aarmondas arrived and I added his info as well.  We still need Michael Dean's up-to-date contact info and lab schedule - got it from Aarmondas, adding it to the blog & calendar.

My own main technical goal for today:  Continue working on the server-side code to remotely initialize the GPS module to the correct current time & location (& any other initialization that is needed to help it acquire satellites & establish a time lock).

Also, need to install the Quartus service packs.  Trying the SP2 install now...  It completed with no errors, except for a USB driver where it said that the already-installed version was newer so I told it not to update that driver.  Now, opening the FEDM_code project (Q:\COSMICi_FEDM.qpf), and letting it update the database files.  Same with the GPS app project (C:\f\DE3\S3\SB+SOPC\GPS_FPGA_app\Quartus_II_Project/DE3_GPSapp/DE3_GPSapp.qpf).  Next time I do a compile, hopefully everything will work.

David, Juan & Aarmondas together made some good progress on the LogicLock task - they now have the high-speed counter in a LogicLock region with analyzed fmax above 500 MHz (actually almost 600).  Aarmondas is working on doing the same for the edge-capture module in the timing-sync datapath, and Darryl will work on the pulse-capture module in the pulseform-capture datapath.

Emailed the students some suggestions for the midterm HW/SW review.

Now:  I want to make sure the system is ready for the students to get trained on how to start it up whenever they need to.

Burned the latest version of the autorun script (with nodeid.txt #1) to the Wi-Fi board for the FEDM (#1).  The board for the CTU is the one labeled #3 (its internal node ID is #0).

Tomorrow I will do a test with both subsystems (CTU+FEDM) together (haven't done that in a little while). (Most of today got eaten up helping manage/guide the students, so I didn't get much done myself...  May work from home tonight though.)

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