Fri., Feb. 24th

Darryl & David are supposed to be here from 2-6 pm today.  Aarmondas is supposed to be here from 4-5. I told George that he really should come in today, since he wasn't here yesterday.  I haven't seen Brian in a while.  Not sure if Juan & M. Dean are coming today or not.

Ray is supposed to be here soon with the replacement hard drive for the Acer.  David can try setting that up.

Some things that can be worked on today:

• Performance improvement:
• Try adding a pipeline stage in the counter fanout.  (Also, disable the path for the currently-unused 6th threshold.)
• Try logic-locking the counter + several pulse_cap's together.
• GPS initialization:
• Test & debug my recent server code changes.  See if the warm-start is enough to trigger acquisition.

George came by and traced out board placements on the plywood.

Antony is here and is going to back up COSMICi's main filesystem (C:\ drive).  We ended up using the Windows utility.  He repartitioned the drive so 500 GB is for use by Windows machines.

One thing I want to check out at some point:  What speed will the old dual-edge triggered versions of our high-speed components run at in a LogicLock region?  If we can get them to run at 500 MHz, then we might be able to actually attain the true 1 ns time resolution that we were originally hoping for.

Didn't get very good results for the dual-edge-triggered carry-save counter, unfortunately (about 300 MHz).  Maybe try again later after we understand what we're doing better...

Meanwhile, we realized some things about LogicLock:

• In some of our earlier tests yielding crazy results like 800 or 900 MHz, actually the time-critical logic was getting compiled away.  So, not all of those earlier results are actually meaningful.  The KEEP attribute does not prevent this; it only prevents internal nodes from getting compiled away by optimizations (not by getting erased entirely due to being unused).
  
• If you simply take a component out of LogicLock and then put it back in, you can get a different speed result, because it can place the "Auto" region in a different place.

Mike got a compilation with 487 MHz for a mockup design including all the high-speed components in the root region, with a pipeline stage for fanning out the counter.  This is nearly fast enough, and might be fast enough at low temperatures (the slow corner didn't meet the timing constraints, but the fast corner did).  However, some caveats:  The pin assignments are not made yet, and also this is not our exact design structure for the high-speed parts, just a quick rough mockup of it.

Trying again with everything in a new Auto region.  This time got 465.12 MHz, with everything shoved over into the left-hand third of the chip.  Try again...

Trying again after deleting the region and recreating it.  Didn't include the clock input and the main output this time.  Got 465.12 again.

Let's try again with NO LogicLock at all.  This time got 487.09 again - the same as when using the root region.  I notice that the layout in this case is non-rectangular.

Finally, let's try once more with putting all the high-speed components into the root region, except this time w/o the main input/output pins included.  Same thing.

Probably a good way to proceed would be to put the real high-speed components into the root region, compile those, then add the rest of the design and recompile, and see if the speed is preserved; and then (if we are still in the ballpark of 490 MHz) test the design with cooling installed to see if it seems to be working.